BRAT Option B504
High Speed Digital Test System
The BRAT Option B504 is a 50 MHz digital test system utilizing Commercial-Off-The-Shelf (COTS) equipment in a modular design. The reconfigurable assembly allows easy access to all of the modules as well as room for expansion/reconfiguring. The interface provides from 320 to 640 high speed digital input/output pins, analog test points, and AC and DC Power.
The BRAT features VXI instrument-on-a-card and modular technologies to provide complex testing capabilities in a compact workstation.
High Speed Dynamic Digital
The I/O pins operate at up to a full 50 MHz data rate. The system offers 64K Vectors per Channel, RAM-Backed and Algorithmic Pattern Generation, NRZ, RZ, RONE, RTC, and RI Output Data Formats, and 16 Stimulus Timing Generators per Module.
Multiple Programmable AC and DC
The power system is a reconfigurable precision power subsystem designed to meet the challenges of high tech ATE.
High Channel Density
Each Module provides 32 stimulus pins and 32 response pins in a single C-size slot. Up to 20 I/O modules may be controlled by a single Control Module. Input and output pins are grouped on separate connectors, providing the most efficient method of interfacing to the UUT. Bidirectional capability is accomplished by externally connecting the input pins to the output pins.
Seven Distinct I/O Memory Types
Each Module contains seven separate memory banks, each 64K vectors in depth, for generating stimulus patterns, expected response patterns, and recording UUT response data. All memory banks operate at full 50 MHz data rates.
The Stimulus Memories consist of the Output, Tri-state, and Algorithmic Output Memories. The Output Memory contains the actual data patterns to be generated to the UUT. Tri-state Memory provides tri-state control which supports bidirectional I/O. The Algorithmic Output Memory determines which algorithmic pattern will be output.
The Response Memories consist of the Expect, Mask, and Algorithmic Expect memories. The Expect Memory contains the expected response data for the UUT and is the basis for input compare operations. The Mask Memory determines which patterns are to be ignored for input response comparison. Algorithmic Expect Memory determines which algorithmic expect pattern will be compared against the UUT input response.
Record Memory is used to store either the UUT response data or the result of the comparison between the UUT response data and the expected response pattern.
Data Formatting with Precise Edge Placement
Stimulus pins may be independently programmed for any of the following data formats: Non-Return to Zero (NRZ), Return to Zero (RZ), Return to One (R1), Return to Complement (RC), and Return to Inhibit/Tri-state (RI).
Each Module contains 16 timing generators for stimulus edge placement and pulse width timing. Output pins can select from 2 pairs of timing generators to define the leading and trailing edges of each signal pin. Groups of eight output pins share an independent set of 2 timing generator pairs for a total of 8 stimulus timing generator sets per card. 100 ps edge placement resolution provides precise UUT timing for bus emulation testing, memory testing, and functional testing.
Response pins can select from 2 response timing generators to define the sample and compare edges, or the 2 response timing generators can be combined together for window compare with glitch detection.
TBASIC (options available)
|DC Power Supply|
|Six Programmable DC Supplies|
|Range:||2 x 0 to 7 Vdc @ 15 A|
|2 x 0 to 20 Vdc @ 10 A|
|2 x 0 to 32 Vdc @ 6.25 A|
|AC Power Supply|
|AC Supply:||(750 VA)|
|Frequency:||Range: 0 to 5 KHz|
|Resolution: 1 Hz|
|(750 VA Max.):||Range: 0 to 130 Vac|
|Resolution: 1 Vac|
|(Options for additional AC and DC supplies are available)|
|AC/DC Voltage:||Range: 30 mV to 300 V|
|Resolution: 10 nV to 100 µV|
|(2/4 Wire):||Range: 30 Ohms to 3 G Ohms|
|Resolution: 10 µ Ohms to 1 K Ohms|
|Frequency:||Range: 10 Hz to 1.5 MHz|
|Period:||Range: 0.025 s to 667 ns|
|92103573-01||Single-Phase AC Programmable Power Supply||1|
|93000074-01||64-Channel Relay Multiplexer||1|
|93000077-01||6 1/2-Digit Digital Multimeter||1|
|94000887-01||DC Power Supply Frame||1|
|94000888-01||0 to 7 V Module for DC Power Supply||2|
|94000889-01||0 to 20 V Module for DC Power Supply||2|
|94000890-01||0 to 32 V Module for DC Power Supply||2|
|96000001-01||50 MHz Digital Interface Timing Module||1|
|96000002-01||50 MHz TTL/CMOS/ECL Pattern Module||10|
|96000014-03||High Power Mainframe - 13 Slots||2|
|96000015-03||AC Current Sharing Power Supply||1|
Options Available for the BRAT Option B504
|Option 100||Option 100 for the BRAT Option B504 includes the following configuration:|
|Increased pin count from 640 to 832|
|96000002-01 50 MHz TTL/CMOS/Pattern Module||1|
|96000007-03 50 MHz Variable I/O Module, 504 Configured, Dual Termination||4|
|96000013-01 Timing Module Extension Card (Dual)||7|
|96000013-03 Timing Module Extension Card (Single)||1|
|Option 500||Option 500 for the BRAT Option B504 (Requires Option 100) includes the following configuration:|
|Additional memory depth of 1 megavector per card of 96 pins totaling 3 cards|
|Programmable target generator for generating low phase noise and low spurious signals|
|Option 600||Option 600 for the BRAT Option B504 allows the system to be operated as a stand-alone test system. It includes the following:|
|94000862-10 Control Assembly|
|96000025-01 PCI-MXI-2 Card|
|96000070-01 Right Angle Point/Right Angle Daisy Chain MXI-2 Cable|
|92103696-05 GPIB Cable|
|In addition, the Runtime software should be moved from the existing front end or an additional Runtime system must be purchased.|